74abt126 ?quad buffer with 3-state outputs ?995 fairchild semiconductor corporation www.fairchildsemi.com 74abt126 rev. 1.4.0 ja n uary 2008 74abt126 quad buffer with 3-state outputs features non-inverting buffers output sink capability of 64ma, source capability of 32ma guaranteed latchup protection high impedance glitch free bus loading during entire power up and power down cycle nondestructive hot insertion capability disable time less than enable time to avoid bus contention general description the abt126 contains four independent non-inverting buffers with 3-state outputs. ordering information device also available in tape and reel. specify by appending suffix letter ??to the ordering number. all packages are lead free per jedec: j-std-020b standard. connection diagram pin description function table h = high voltage level l = low voltage level z = high impedance x = immaterial order number package number package description 74abt126csc m14a 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow 74abt126csj m14d 14-lead small outline package (sop), eiaj type ii, 5.3mm wide 74abt126cmtc mtc14 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pin names description a n , b n inputs o n outputs inputs output a n b n o n h l l h h h l x z
?995 fairchild semiconductor corporation www.fairchildsemi.com 74abt126 rev. 1.4.0 2 74abt126 ?quad buffer with 3-state outputs absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. note: 1. either voltage limit or current limit is sufficient to protect inputs. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter rating t stg storage temperature ?5? to +150? t a ambient temperature under bias ?5? to +125? t j j unction temperature under bias ?5? to +150? v cc v cc pin potential to ground pin ?.5v to +7.0v v in input voltage (1) ?.5v to +7.0v i in input current (1) ?0ma to +5.0ma v o v oltage applied to any output disabled or power-off state ?.5v to 5.5v high state ?.5v to v cc current applied to output in low state (max.) twice the rated i ol (ma) dc latchup source current (across comm operating range) ?00ma over voltage latchup (i/o) 10v symbol parameter rating t a f ree air ambient temperature ?0? to +85? v cc supply voltage +4.5v to +5.5v ? v / ? t minimum input edge rate data input 50mv/ns enable input 100mv/ns
?995 fairchild semiconductor corporation www.fairchildsemi.com 74abt126 rev. 1.4.0 3 74abt126 ?quad buffer with 3-state outputs dc electrical characteristics notes: 2. guaranteed, but not tested. 3. for 8-bit toggling, i ccd < 0.8ma/mhz. symbol parameter v cc conditions min. typ. max. units v ih input high voltage recognized high signal 2.0 v v il input low voltage recognized low signal 0.8 v v cd input clamp diode voltage min. i in = ?8ma ?.2 v v oh output high voltage min. i oh = ?ma 2.5 v i oh = ?2ma 2.0 v ol output low voltage min. i ol = 64ma 0.55 v i ih input high current max. v in = 2.7v (2) 1 a v in = v cc 1 i bvi input high current breakdown t est max. v in = 7.0v 7 a i il input low current max. v in = 0.5v (2) ? ? v in = 0.0v ? v id input leakage test 0.0 i id = 1.9?, all other pins grounded 4.75 v i ozh output leakage current 0?.5v v out = 2.7v, oe n = 2.0v 10 ? i ozl output leakage current 0?.5v v out = 0.5v, oe n = 2.0v ?0 a i os output short-circuit current max. v out = 0.0v ?00 ?75 ma i cex output high leakage current max. v out = v cc 50 ? i zz bus drainage test 0.0 v out = 5.5v, all others gnd 100 ? i cch po w er supply current max. all outputs high 50 ? i ccl po w er supply current max. all outputs low 15 ma i ccz po w er supply current max. oe n = v cc , all others at v cc or ground 50 ? i cct additional i cc /input outputs enabled max. v i = v cc ?2.1v 1.5 ma outputs 3-state enable input v i = v cc ?2.1v 1.5 ma outputs 3-state data input v i = v cc ?2.1v, all others at v cc or ground 50 ? i ccd dynamic i cc no load (2) max. outputs open, oe n = gnd (3) , one-bit toggling, 50% duty cycle 0.1 ma/ mhz
?995 fairchild semiconductor corporation www.fairchildsemi.com 74abt126 rev. 1.4.0 4 74abt126 ?quad buffer with 3-state outputs ac electrical characteristics capacitance note: 4. c out is measured at frequency f = 1mhz, per mil-std-883, method 3012. symbol parameter t a = +25?, v cc = +5v, c l = 50pf t a = ?0? to +85? v cc = 4.5v?.5v c l = 50pf units min. typ. max. min. max. t plh propagation delay, data to outputs 1.0 4.4 1.0 4.4 ns t phl 1.0 4.6 1.0 4.6 t pzh output enable time 1.0 6.5 1.0 6.5 ns t pzl 1.0 6.5 1.0 6.5 t phz output disable time 1.0 5.8 1.0 5.8 ns t plz 1.0 5.5 1.0 5.5 symbol parameter conditions t a = 25? typ. units c in input capacitance v cc = 0v 5.0 pf c out (4) output capacitance v cc = 5.0v 9.0 pf
?995 fairchild semiconductor corporation www.fairchildsemi.com 74abt126 rev. 1.4.0 5 74abt126 ?quad buffer with 3-state outputs physical dimensions figure 1. 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchild s worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductor s online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ land pattern recommendation notes: unless otherwise specified a) this package conforms to jedec ms-012, variation ab, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x145-14m e) drawing conforms to asme y14.5m-1994 f) drawing file name: m14arev13 pin one indicator 8 0 seating plane detail a scale: 20:1 gage plane 0.25 x45 1 0.10 c c b c a 7 m 14 b a 8 see detail a 5.60 0.65 1.70 1.27 8.75 8.50 7.62 6.00 4.00 3.80 (0.33) 1.27 0.51 0.35 1.75 max 1.50 1.25 0.25 0.10 0.25 0.19 (1.04) 0.90 0.50 0.36 r0.10 r0.10 0.50 0.25
?995 fairchild semiconductor corporation www.fairchildsemi.com 74abt126 rev. 1.4.0 6 74abt126 ?quad buffer with 3-state outputs physical dimensions (continued) figure 2. 14-lead small outline package (sop), eiaj type ii, 5.3mm wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchild s worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductor s online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/
?995 fairchild semiconductor corporation www.fairchildsemi.com 74abt126 rev. 1.4.0 7 74abt126 ?quad buffer with 3-state outputs physical dimensions (continued) figure 3. 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchild s worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductor s online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ c. dimensions are exclusive of burrs, mold flash, and tie bar extrusions f. drawing file name: mtc14rev6 r0.09 min 12.00 top & botto m 0.43 typ 1.00 d. dimensioning and tolerances per ansi y14.5m, 1982 r0.09min e. landpattern standard: sop65p640x110-14m 0.65 6.10 1.65 0.45 a. conforms to jedec registration mo-153, variation ab, ref note 6 b. dimensions are in millimeters
?995 fairchild semiconductor corporation www.fairchildsemi.com 74abt126 rev. 1.4.0 8 trademarks th ef ollowing includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its global s ubsidiaries, and is not intended to be an exhaustive list of all such trademarks. acex build it now coreplus crossvolt ctl current transfer logic ecospark ezswit ch * fairchild fairchild semiconductor fact quiet series fact fast fastvcore flashwriter ? fps frfet global power resource sm green fps green fps e-series gto i-lo intellimax isoplanar m egabuck mi crocoupler microfet micropak mi llerdrive mo ti on-spm optologic optopl anar pdp-spm pow er220 pow er247 poweredge power-spm po we rtrench pr ogrammable active droop qfet qs qt optoelectronics quiet series rapidconfigure smart start spm stealth s uperfet su persot -3 s upersot -6 s upersot -8 syncfet the power franchise tinyboost tinybuck tinylogic tinyopto tinypower tinypwm tinywire serdes uhc ultra f rfet unifet vcx *ezswi tch and flashwriter are trademarks of system general corporation, used under license by fairchild semiconductor. disc laimer fa i rchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any pro duct or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these speci fications do not expand t he terms of fairchild? wo rl dw ide terms and conditions, specifically the warranty therein, which covers these products. life support policy fa i rchild s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems wh ic h, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform wh en properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. pr oduct status definitions defi nition of terms da tasheet identification product status definition ad vance information form first production ative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. pr eliminary this datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to ma ke c hanges at any time without notice to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve the des i gn. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. rev. i32 74abt126 ?quad buffer with 3-state outputs
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